The semiconductor industry requires processes for achieving higher device density within a given die area. This is particularly true in memory circuit fabrication, in which the number and density of memory cells on a given chip have dramatically increased. The increase in density is a result of downsizing of the individual semiconductor devices, due partly to advances in photolithography and directional (anisotropic) plasma etching. As the horizontal device feature sizes continue to decrease to submicron dimensions, it is necessary to use self-alignment techniques to relax the alignment requirements and improve critical dimension (CD) control. One such technique is called a self-align contact (SAC) etch, in which a pair of adjacent gate stacks are utilized to align an etched opening in an insulating layer.
A conventional SAC process includes first providing a substrate on which there are at least two memory cells (such as MOS devices or flash memory cells), then forming an insulating layer, such as silicon oxide, on the substrate. Each of the two or more memory cells includes a polysilicon gate and spacers on the sidewalls of the gate. The two cells have a common source/drain region located between the gates of the cells. The insulating layer is patterned to form a self-align contact opening which exposes the common source/drain region. A conductive layer is deposited in the self align contact opening to form a contact. SAC etch processes primarily involve dry or plasma etches, typically utilizing a CxFy (x>1)-type plasma chemistry, such as, for example C4F8, C5F8, or C4F6 in combination with other diluent gases.
The increase in packing density also places increased demands on many aspects of the fabrication process. Alignment of features from one level to the next is critically important, particularly the alignment of contact holes with underlying structures. The miniaturization of the devices makes the formation of interconnect structures difficult. To maintain sufficient electrical communication, the interconnect structure must be formed in precise alignment with the underlying active region. At the same time, the area of the interconnect structure interfacing with the active area must be maximized. Thus, as device sizes decrease, there is less room for misalignment errors of the interconnect structure.
Moreover, misalignment during an etch process can create problems resulting from the unintended etching or removal of an oxide seam (or spacer) along a gate stack, which forms between the gate stack and nitride spacers when spacer process formation includes the deposition of an oxide liner. In a flash cell, for example, if the misaligned SAC etch removes the oxide seam, metal will be deposited during subsequent plug fill metallization steps into the space where the seam previously was located, thereby causing the control to become shorted to both the floating gate and the substrate. FIGS. 1-3 illustrate this problem.
FIG. 1 depicts a pair of typical flash cell gate stacks 1 positioned adjacent to each other on a substrate 2 at an intermediate stage prior to SAC etching. Each stack includes a tunnel oxide layer 3 positioned on top of the substrate 2. A polysilicon floating gate 4 is positioned on top of the tunnel oxide layer 3 and an oxide/nitride/oxide (ONO) layer 5 is positioned on top of floating gate 4. A polysilicon control gate 6 is typically formed on top of the ONO layer 5 with a tungsten silicide layer 7 formed on top of the control gate 6. A cap 8, which is typically either nitride or TEOS is positioned on the tungsten silicide layer 7. Between the gate stacks is the area 9 in which the contact will be etched into the substrate.
FIGS. 2A-2D illustrate processing steps that may be performed subsequent to the intermediate stage illustrated in FIG. 1. First, an oxide layer 10, preferably a TEOS layer with a thickness of between about 50 Å and about 300 Å, more preferably, 100 and 200 Angstroms, is deposited over the surface of the device (FIG. 2A), to include sidewall S/D oxidation. Next, dry etching is used to remove horizontal TEOS surfaces, leaving vertical surfaces to form oxide spacers (also referred to herein as seams) 11, along the gate stack edge (FIG. 2B). To form a nitride spacer, a nitride layer 12 is deposited over the surface of the device, as shown in FIG. 2C. To complete nitride spacer formation, a dry etch is used, resulting in gate stacks having oxide seams (spacers) 11 separating nitride spacers 13 from gate stack 1 (FIG. 2D). The oxide seams 11 are exposed at the top 14, which can present a problem during the subsequent SAC etch process.
Following a first dielectric layer deposition, a self-align contact etch is used to remove the dielectric from the common region between the gate stacks to prepare the contact region 15 for metal deposition. FIG. 3 illustrates a problem that occurs when the self-align contact etch 17 is misaligned so as to hit a gate stack, rather than merely the contact region between adjacent gate stacks. Because the first level dielectric 16 and the exposed oxide seam 11 are composed of the same material, the etch plasma chemistry, which is selective to this material, etches out the oxide seam as well as the intended dielectric, leaving a void where the seam was. Once the seam is etched out, the resulting void would then be filled with metal. Because the metal deposited in the vertical space where the oxide seam had been is conductive, the control gate would be shorted to the floating gate and to the substrate (in a flash memory cell for example), or the gate would be shorted to the substrate (in a device other than a flash cell, such as, for example, a standard MOS transistor). This shorting results in a non-functional device.
There is thus a need for a method which mitigates or eliminates the above disadvantages. In particular, there is a need for a method which prevents problems, such as shorting between gate stack components, that occur when a misaligned self-align contact etch unintentionally removes an oxide seam or spacer.